Power semiconductor device with small contact footprint and the preparation method

ABSTRACT

A power semiconductor package with a small footprint and a preparation method thereof are disclosed. The first semiconductor chip and second semiconductor chip are attached on the front and back sides of a die paddle. Conductive pads are then attached on the electrodes at the top surfaces of the first and second semiconductor chips flowed by the formation of a plastic package body covering the die paddle, first and second semiconductor chips, the conductive pads, where a side surface of a conductive pad is exposed from a side surface of the plastic package body.

FIELD OF PRESENT INVENTION

The present invention mainly relates to a power semiconductor package, and more particularly to a power semiconductor device with a small contact footprint and a preparation method thereof.

BACKGROUND OF RELATED ART

In the applications of a power transistor, the overall dimension and heat dissipation are two important parameters of the device. The heat dissipation of the device is generally improved by exposing part of the electrode of the transistor, but the implementation process is very complicated. In switching circuits such as synchronous buck converters, half bridge converter and inverters, two power MOSFETs are switched in complementary fashion.

As shown in FIG. 1A, U.S. Pat. No. 7,485,954 discloses a stacked dual MOSFET package. The integrated circuit package includes a high side MOSFET die 230 coupled to a first conductive tab 210 such that a drain of the high side MOSFET die 230 is attached on and electrically connected to the first conductive tab 210; a second conductive tab 243 attached on and electrically connected to a source of the high side MOSFET die 230; and a low side MOSFET die 250 coupled to the second conductive tab 243 such that a drain of the low side MOSFET die 250 is attached on and electrically connected to the second conductive tab 243. The high side MOSFET die 230, the low side MOSFET die 250, the first conductive tab 210 and the second conductive tab 243 are stacked so that the second conductive tab 243 electrically contacts with a top electrode of the high side MOSFET die 230 and a bottom electrode of the low side MOSFET die 250, and the bottom surface 215 of the conductive tab 210 and the bottom surface 247 of the conductive tab 240 are coplanar.

Furthermore, as shown in FIG. 1B, U.S. Pat. No. 8,519,520 discloses a semiconductor device package with a high-side chip and a low-side chip and a manufacturing method thereof. In the device, the low-side chip 200 and the high-side chip 300 are attached to the two opposite sides of a lead frame respectively, so that a bottom drain electrode of the low-side chip 200 is electrically connected to a top side of a die paddle 110 and a top source electrode of the high-side chip 300 is electrically connected to a bottom side of the die paddle 110 through solder balls 311. A top gate electrode of the low-side chip 200 is connected to a pin 122 of the lead frame by a metal clip 230 and the top gate electrode of the high-side chip 300 are connected to a pin 123 of the lead frame, where the pins 122 and 123 are coplanar. In the invention, the stacking structure of the low-side chip 200, the die paddle 110 of a lead frame 100 and the high-side chip 300 reduces the package size. After encapsulating the low-side chip 200, the die paddle 110 of a lead frame 100 and the high-side chip 300 with a package body 400, a metal layer 320 (or a conductive layer 320′) covering the back side of the high-chip 300 is exposed outside of a package body 400 at the bottom surface of the semiconductor device to improve the heat dissipation of the device.

The prior art semiconductor device packages of FIG. 1A and FIG. 1B cannot provide the best heat dissipation and the device has a relatively large footprint, for example the size of a pin or a metal clip cause the device to occupy a large area on a PCB circuit board.

It is within this context that embodiments of the present invention arise.

BRIEF DESCRIPTION OF THE DRAWINGS

Objects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings in which:

FIG. 1A and FIG. 1B are schematic diagrams illustrating the conventional power semiconductor packages.

FIG. 2A to FIG. 2I are schematic diagrams showing the steps of a method for preparing a stacked power semiconductor device with a small contact footprint at the device's side surface according to an embodiment of the present invention.

FIG. 3A to FIG. 3C are schematic diagrams showing the step of mounting the power semiconductor device of FIG. 2I on a PCB circuit board.

FIG. 4A to FIG. 4B are schematic diagrams showing the power semiconductor devices with heat sinks attached thereto.

FIG. 5A to FIG. 5B are schematic diagrams showing a power semiconductor device with the die paddle not exposed outside of the plastic package body.

FIG. 6A to FIG. 6B are schematic diagrams showing a power semiconductor device with the top surface of the first conductive pads attached on the top surfaces of the first and second semiconductor chips not exposed outside of the plastic package body.

FIG. 7A to FIG. 7D are schematic diagrams showing the alternative steps of the method for preparing a power semiconductor device of FIG. 2I.

DESCRIPTION OF THE SPECIFIC EMBODIMENTS

As shown in FIG. 2A, a lead frame 100 includes a plurality of die paddles 101 and a plurality of positioning holes 105 formed at the edge of the lead frame 100 (the number or orientation of the positioning holes 105 are shown in this Fig. as an example). The die paddle 101 is generally in a square structure, which has a front side and a back side opposed to each other. It is well known in the art that the die paddle 101 is connected together within the lead frame 100 or to the support bars of the lead frame 100 through a plurality of connecting ribs. The lead frame 100 is also defined as the first lead frame.

As shown in FIG. 2B, with the existing surface mount technology, a plurality of first semiconductor chips 201 are attached on the front side of the plurality of die paddle 101 one to one via conductive bonding material (such as solder paste, conductive paste and the likes or an eutectic solder). The first semiconductor chip 201 is a vertical power MOSFET, which has some electrodes at the top surface and one electrode at the bottom surface and the current flows from the top to the bottom or vice versa. The first semiconductor chip 201 is attached on the front side of the die paddle 101, where the bottom electrode of the first semiconductor chip 201 is electrically connected with the die paddle 101. It should be noted that in this step, both the lead frame 100 and each die paddle 101 face up.

In FIG. 2C, the lead frame 100 is flipped so that the back side of the lead frame faces up and the front side thereof faces down. As such, each die paddle 101 and the first semiconductor chip 201 attached thereto are also flipped. Then, a plurality of second semiconductor chips 202 are also attached to the back side of the plurality of die paddle 101 one to one. The second semiconductor chip 202 is also a vertical power MOSFET. The bottom of the second semiconductor chip 202 is attached to the back side of the die paddle 101, where the bottom electrode of the second semiconductor chip 202 is electrically connected to the back side of the die paddle 101. As a result, both the front side and the back side of each die paddle 101 are correspondingly attached with one first semiconductor chip 201 and one second semiconductor chip 202.

FIG. 2D-1 is a perspective view illustrating one die paddle 101 with one first semiconductor chip 201 attached on its front side and one second semiconductor chip 202 attached on it back side for demonstration, but it should be emphasized that no cutting step is performed for the lead frame 100 at this stage. As shown in FIG. 2D-1, an electrode 201 a and an electrode 201 b are formed at the top surface of the first semiconductor chip 201 (the electrode at the back of the first semiconductor chip 201 is not shown). Similarly, an electrode 202 a and an electrode 202 b are formed at the top surface of the second semiconductor chip 202 as shown in FIG. 2D-2 (the electrode at the back of the second semiconductor chip 202 is not shown).

In FIG. 2E-1, a lead frame 300, which is defined as the second lead frame, includes a plurality of conductive units 301, each of which comprises one or more conductive pads separated from each other; for example, in one embodiment, the conductive unit 301 comprises a first conductive pad 301 a and a second conductive pad 301 b. The first conductive pad 301 a is larger than the second conductive pad 301 b. The first conductive pad 301 a has an L-shape with a notch formed at one corner, and the second conductive pad 301 b is arranged inside the notch so that the overall size of the conductive unit 301 is minimized. It is well known in the art that the first conductive pad 301 a and the second conductive pad 301 b are connected together within the lead frame 300 through a plurality of connecting ribs. The lead frame 300 also includes positioning holes 305 formed at the edge of the lead frame 300 in positions corresponding to positioning holes 105.

As shown in FIG. 2E-2, a third lead frame 400, similar to the lead frame 300, includes a plurality of conductive units 401, each of which comprises one or more conductive pads separated from each other; for example, in one embodiment, the conductive unit 401 comprises a first conductive pad 401 a and an a second conductive pad 401 b, where the first conductive pad 401 a is larger than the second conductive pad 401 b. The first conductive pad 401 a has an L-shape with a notch formed at one corner, and the second conductive pad 401 b is arranged inside the notch so that the overall size of the conductive unit is minimized. The third lead frame 400 also includes positioning holes 405 formed at the edge of the lead frame 400 in positions corresponding to positioning holes 105.

As shown in FIG. 2F, the second lead frame 300 with the plurality of conductive units 301 is mounted on the plurality of first semiconductor chips 201, where each conductive unit 301 is mounted on each first semiconductor chip 201 so that one first conductive pad 301 a is aligned with and attached on the electrode 201 a at the top surface of the first semiconductor chip 201 and one second conductive pad 301 b is aligned with and attached on the electrode 201 b at the top surface of the first semiconductor chip 201. Thus, the third lead frame 401 with the plurality of conductive units 401 is mounted on the plurality of second semiconductor chips 202, where one conductive unit 401 is mounted on each second semiconductor chip 202 so that one conductive pad 401 a is aligned with and attached on the electrode 202 a at the top surface of the second semiconductor chip 202 and one conductive pad 401 b is aligned with and attached on the electrode 202 b at the top surface of the second semiconductor chip 202. In a preferred embodiment, the lead frame 100 of FIG. 2C may be flipped back, where the front surface of the lead frame 100 and the attached first semiconductor chip 201 face up, following with the mounting of the lead frame 300 on the top surface of the first semiconductor chips, and then the lead frame 100 is flipped again, where the back surface of the lead frame 100 and the attached second semiconductor chips 202 face up, following with the mounting of the lead frame 400 on the second semiconductor chips 202. Alternatively, the lead frame 400 is directly mounted on the second semiconductor chips 202 of the lead frame of FIG. 2C firstly, and then the lead frame 100 is flipped back (the front surface of the lead frame 100 and the attached first semiconductor chip 201 face up), following with the mounting of the lead frame 300 on the first semiconductor chips 201. The cross-sectional drawing of FIG. 2F illustrates that the lead frame 300, the lead frame 400 and the lead frame 100 are parallel with each other with the first and second semiconductor chips 201, 201 sandwiched in between. At this time, one first semiconductor chip 201 and one second semiconductor chip 202 are attached to each die paddle 101, one conductive unit 301 is attached to each first semiconductor chip 201, and one conductive unit 401 is attached to each second semiconductor chip 202. FIG. 2G is a perspective view for demonstration without a cutting step of the lead frame 100, the lead frame 300 and the lead frame 400 showing one die paddle 101, the first semiconductor chip 201 and the second semiconductor chip 202 attached to its front side and its back side respectively, the conductive unit 301 and the conductive unit 401 attached on the top surfaces of the first semiconductor chip 201 and the second semiconductor chip 202 respectively.

As shown in FIG. 2G and FIG. 2D-1, one first conductive pad 301 a is attached on the electrode 201 a at the top surface of the first semiconductor chip 201 and one second conductive pad 301 b is attached on the electrode 201 b at the top surface of the first semiconductor chip 201. One first conductive pad 401 a is attached on the electrode 202 a at the top surface of the second semiconductor chip 202 and one second conductive pad 401 b is attached on the electrode 202 b at the top surface of the second semiconductor chip 202. The electrodes at the bottom surfaces of the first semiconductor chip 201 and the second semiconductor chip 202 are electrically connected to two opposite sides of the die paddle 101 respectively. In a power management system, the first semiconductor chip 201 and the second semiconductor chip 202 are functioned as a pull-up transistor and a pull-down transistor respectively. Although the size of the first semiconductor chip 201 is slightly different from the size of the second semiconductor chip 202 the electrode 201 a of the first semiconductor chip 201 and the electrode 202 a of the second semiconductor chip 202 are parallel to the plane of the die paddle 101. The electrode 201 b of the first semiconductor chip 201 and the electrode 202 b of the second semiconductor chip 202 are also parallel to the plane of the die paddle 101. As a result, the first conductive pad 301 a and the first conductive pad 401 a are also parallel to the plane of the die paddle 101 and the second conductive pad 301 b and the second conductive pad 401 b are parallel to the plane of the die paddle 101.

In FIG. 2G, the thickness of the first and second conductive pads 301 a and 301 b on the respective electrodes at the top surface of the first semiconductor chip 201 (or the thickness of the conductive pads 401 a and 401 b on the respective electrodes at the top surface the second semiconductor chip 202) is unequal. In a preferred embodiment, the first conductive pad 301 a on the electrode 201 a of the first semiconductor chip 201 is thicker than the second conductive pad 301 b on the electrode 201 b, and the first conductive pad 401 a on the electrode 202 a of the second semiconductor chip 202 is thicker than the second conductive pad 401 b on the electrode 202 b.

As shown in FIG. 2H, the bottom side of the first conductive pad 301 a is attached to the electrode 201 a of the first semiconductor chip 201 and the bottom side of the second conductive pad 301 b is attached to the electrode 201 b of the first semiconductor chip 201. The bottom side of the first conductive pad 401 a is attached to the electrode 202 a of the second semiconductor chip 202 and the bottom side of the second conductive pad 401 b is attached to the electrode 202 b of the second semiconductor chip 202. Thus, after a step of forming the plastic package, for example, a plastic package layer 501 of epoxy resin or molding compound is formed covering the lead frame 100, the lead frame 300 and the lead frame 400, as well as each first semiconductor chip 201 and each second semiconductor chip 202. The plastic package layer 501 is then ground to expose the top surfaces of the first conductive pad 301 a of each conductive unit 301 and the first conductive pad 401 a of each conductive unit 401, while the top surfaces of the thinner second conductive pad 301 b and the thinner second conductive pads 401 b are covered by the plastic package layer 501.

As shown in FIG. 2H and FIG. 2I, a side surface 101′ of each die paddle 101, a side surface 301′a of the first conductive pad 301 a, and a side surface 401′a of the first conductive pad 401 a are located in the co-plane 508. In addition, a side surface 301′b of the second conductive pad 301 b, and a side surface 401′b of second conductive pad 401 b are also located in the co-plane 508. Therefore, before forming the plastic package layer 501, the side surfaces 101′ of the die paddle 101 and the side surfaces 301′a, 401′a, 301′b and 401′b of the conductive pads 301 a, 401 a, 301 b and 401 b respectively must be located in the co-plane 508. As such, after the plastic package layer 501 is formed, the lamination including the lead frame 100, the lead frame 300 and the lead frame 400 and the plastic package layer 501 is cutting to obtain individual power semiconductor devices 555, one of which is shown in FIG. 2I, with the side surfaces 301′a, 401′a, 301′b, 401′b and 101′ exposed outside of a cutting side surface 500C of the plastic package body 500 formed by cutting the plastic package layer 501 along the co-plane 508. If the side surfaces of the die paddle 101 and the conductive pads 301 a, 401 a, 301 b,401 b are not originally located in a same plane, the co-plane side surfaces 101,301′a, 401′a, 301′b, 401′b can be formed by cutting the die paddle 101 and the conductive pads 301 a, 401 a, 301 b, 401 b along a cutting surface, i.e., the side surface 500C. As such, the cut side surfaces 101′, 301′a, 401′a, 301′b, 401′b are coplanar with the cutting surface of the plastic package body 500, i.e., the side edge surface 500C.

In the steps of FIG. 2H to FIG. 2I, the individual power semiconductor device 555 as shown in FIG. 2I are separated by cutting the lamination (comprising the lead frame 100, the lead frame 300, the lead frame 400 and the plastic package layer 501) between adjacent die paddles 101 along a cutting line 554 as shown in FIG. 2H. Each die paddle 101 and the first semiconductor chip 201 and the second semiconductor chip 202 attached thereto are covered by the plastic package body 500 formed by cutting the plastic package layer 501, which further covers the first conductive pad 301 a and the conductive pad 301 b at the top surface of the first semiconductor chip 201 attached on the die paddle 101 and the first conductive pad 401 a and the second conductive pad 401 b at the top surface of the second semiconductor chip 202 attached on the die paddle 101. In an embodiment, if the top surfaces of the first conductive pad 301 a and the first conductive pad 401 a are exposed outside of the plastic package layer 501 the top surfaces of the first conductive pad 301 a and the first conductive pad 401 a are exposed from the top and bottom surfaces 500A and 500B of the plastic package body 500. In addition, only the side surface 101′ of the die paddle 101 is exposed outside of the side edge surface 500C of the plastic package body 500, i.e., the other three side surfaces of the die paddle are totally encapsulated by the plastic package body.

As shown in FIG. 3A, a PCB (Printed Circuit Board) 600 includes bonding pads 604 a, 604 b, 603 a, 603 b and 601 arranged on the contact surface of the PCB 600. The layout of these bonding pads is correspondingly the same as the layout the exposed side surfaces 301′a, 301′b, 401′a, 401′b and 101′ on the side surface 500C of the power semiconductor device 555 (shown in FIGS. 2I and 3B). As shown in FIG. 3A and FIG. 3B, the size and the shape of the bonding pads 604 a, 604 b are essentially consistent with those of the exposed side surface 401′a, 401′b of the conductive pads 401 a and 401 b respectively. The size and the shape of the bonding pads 603 a, 603 b are essentially consistent with those of the exposed side surfaces 301′a, 301′b of the conductive pads 301 a and 301 b respectively. In addition, the size and the shape of the bonding pad 601 are essentially consistent with those of the exposed side surface 101′ of the die paddle 101. As shown in FIG. 3C, the power semiconductor device 555 is mounted on the PCB via the surface mount technology, where the same size and shape bonding pad and the exposed side surface of the conductive pad are aligned with and welded with each other with the solder paste. At this time, both the top side 500A and the bottom side 500B of the plastic package body 500 are perpendicular to the contact surface of the PCB. With the traditional technology, if the top side 500A and the bottom side 500B of the plastic package body 500 are mounted on the PCB, it is required a larger area of the contact surface of the PCB because the areas of the top side 500A and the bottom side 500B of the plastic package body 500 is much larger than that of the side surface 500C, resulting in larger-sized device package. In the present invention, the top side 500A and the bottom side 500B of the power semiconductor device 555 are perpendicular to the contact surface of the PCB, and the smaller side surface 500C is mounted on the contact surface of the PCB, thus greatly reducing the occupied PCB area; therefore, providing a device with the small contact footprint.

In the embodiments of FIG. 4A and FIG. 4B, an L-shaped heat sink 700 a is attached to the exposed top surface of the first conductive pad 301 a, where the shape and size of heat sink 700 a are adjusted to match to those of the first conductive pad 301 a, so that the L-shaped heat sink 700 a can be in alignment with and overlapped with the first conductive pad 301 a to achieve a maximum heat dissipation. In addition, an extension part 700 b is perpendicular and connected to and extending out from the heat sink 700 a at one edge 700 c of the heat sink 700 a, where the edge 700 c of the heat sink 700 a is flush with the side surface 500C of the plastic package body 500. In FIG. 4B, the power semiconductor device 555 is perpendicularly mounted on the contact surface of the PCB, and the extension part 700 b is mounted on the contact surface of the PCB. The extension part 700 b at two opposite sides of the power semiconductor device 555 are also electrically connected to the bonding pad 604 a and the bonding pad 603 a through a conductive binding material, such as solder paste, to increase the contact area between the first conductive pad 401 a and the bonding pad 604 a and the contact area between the first conductive pad 301 a and the bonding pad 603 a; as well as enhance the attach between the power semiconductor device 555 and the PCB. The extension part 700 b is also used for heat dissipation of the device.

In one embodiment, when the first semiconductor chip 201 and the second semiconductor chip are MOSFETs, where the electrode 201 b is the gate, the electrode 201 a is the drain and the electrode at the back of the first semiconductor chip 201 is the source thereof (FIG. 2D-1), and the electrode 202 b of the second semiconductor chip 202 is the gate, the electrode 202 a is the source and the electrode at the back of the second semiconductor chip 202 is the drain (FIG. 2D-2), in the device of FIG. 2I, the side surface 101′ of the die paddle 101 is required to be exposed outside, and the die paddle 101 is used as a coupling node LX between the pull-up transistor and the pull-down transistor to output voltage. In another embodiment, when the electrode 201 b of the first semiconductor chip 201 is the gate, the electrode 201 a is the source and the electrode at the back of the first semiconductor chip 201 is the drain (FIG. 2D-1), and electrode 202 b of the second semiconductor chip 202 is the gate, the electrode 202 a is the source and the electrode at the back of the second semiconductor chip 202 is the drain (FIG. 2D-2), the side surface 101′ of the die paddle 101 is not required to be exposed outside of the side edge surface 500C of the device which is described in FIG. 5B.

In one embodiment shown in FIG. 5A and FIG. 5B, the side surfaces 301′a and 301′b of the conductive pads 301 a and 301 b of the first semiconductor chip 201 and the side surfaces 401′a and 401′b of the conductive pads 401 a and 401 b attached on the second semiconductor chip 202 are located in the co-plane 508′ excepting that the side surface 101′ of the die paddle 101 is not located in the co-plane 508′, in fact, the side surface 101′ is close to the co-plane 508′ and not extending out to the co-plane 508′. In the step of cutting the lamination along the co-plane 508′ to separate individual devices 555, the side surfaces 301′a, 301′b, 401′a and 401′b of the conductive pads 301 a, 301 b, 401 a and 401 b respectively are exposed outside of the side edge surface 500C of the plastic package body 500, but the die paddle 101 is completely encapsulated inside the plastic package body 500. In one embodiment, when the first semiconductor chip 201 and the second semiconductor chip are MOSFETs, where the electrode 201 b is the gate, the electrode 201 a is the source and the electrode at the back of the first semiconductor chip 201 is the drain (FIG. 2D-1) and the electrode 202 b of the second semiconductor chip 202 is the gate, the electrode 202 a is the source, the electrode at the back of the second semiconductor chip 202 is the drain (FIG. 2D-2), the first semiconductor chip 201 and the second semiconductor chip 201 are configured with a common drain. In the case that the side surfaces 301′a, 401′a, 301′b,401′b of the conductive pads 301 a, 401 a, 301 b,401 b are not originally located in a same plane, the co-plane side surfaces 301′a, 401′a, 301′b, 401′b can be formed by cutting the conductive pads 301 a, 401 a, 301 b, 401 b along a cutting surface, i.e., the side surface 500C. As such, the cut side surfaces 301′a, 401′a, 301′b, 401′b are coplanar with the cutting surface of the plastic package body 500, i.e., the side edge surface 500C. The side surface 101′ of the die paddle 101 is close to the cutting surface 500C but is not exposed from the cutting surface 500C.

In another embodiment, as shown FIG. 6A and FIG. 6B, the second lead frame 300 and/or the third lead frame 400 can be totally covered by the plastic package layer 501. If each conductive unit 301 in the second lead frame 300 and each conductive unit 401 in the second lead frame 400 are covered by the plastic package layer 501, the top surface of the conductive pad 301 a and/or the top surface of the conductive pad 401 a may not be exposed outside of the top side and bottom side of the plastic package layer 501 respectively. As shown in FIG. 6B, the respective top surfaces of the conductive pads 301 a, 301 b, 401 a and 401 b are totally covered by the plastic package body 500, but the side surface of each conductive pad is exposed outside of the side surface 500C of the plastic package body 500 (similar to FIG. 2I).

FIG. 7A to FIG. 7D illustrate the alternative steps of a method forming the power device 555 that can be replaced for those in FIG. 2A to FIG. 2F. In this embodiment, the lead frame 100 is not required to be flipped. In FIG. 7A, the process starts with the lead frame 300, where its bottom side and each conductive pad thereof face up. The first semiconductor chip 201 is flipped and attached on the conductive unit 301 of the lead frame 300, so that the first conductive pad 301 a is aligned with and attached to the electrode 201 a at the top surface of each first semiconductor chip 201, and the second conductive pad 301 b is aligned with and attached to the electrode 201 b at the top surface of each first semiconductor chip 201. As shown in FIG. 7B-1 and FIG. 7B-2, the first lead frame 100 with the plurality of die paddles 101 is mounted on the plurality of first semiconductor chips 201, so that the electrode at the back of each first semiconductor chip 201 is aligned with, attached and electrically connected to the back side of the die paddle 101. As shown in FIG. 7C-1 and FIG. 7C-2, the second semiconductor chip 202 is then attached to the front side of each die paddle 101, where the electrode at the bottom surface of the second semiconductor chip 202 is attached and electrically connected to the front side of the die paddle 101. As shown in FIG. 7D, the third lead frame 400 with the plurality of conductive units 401 is mounted on the plurality of second semiconductor chips 202, so that the first conductive pad 401 a is aligned with and attached to the electrode 202 a at the top surface of each second semiconductor chip 202 and the second conductive pad 401 b is aligned with and attached to the electrode 202 b at the top surface of each second semiconductor chip 202. The structure shown in FIG. 7D, comprising the first semiconductor chip 201, the second semiconductor chip 202, the lead frame 100, the lead frame 300 and the lead frame 400, maybe flipped to obtain the structure as shown in FIG. 2F and FIG. 2G (but in fact, it is unnecessary to flip), and the other subsequence steps of the method as shown in FIG. 2H to FIG. 2I are then performed to complete the process of making the device 555.

The layouts of the positioning holes 105 arranged at the edge of the first lead frame 100, the positioning holes 305 arranged at the edge of the second lead frame 300 and the positioning holes 405 arranged at the edge of the third lead frame 400 are the same so that the second and third lead frames 300, 400 may be precisely aligned with and positioned with the first lead frame 100 when the second lead frame and the third lead frame 300, 400 are mounted on the first and second semiconductor chips 201, 202 attached on front and back sides of the first lead frame. In other words, the self-alignment is performed along the vertical direction, for example, a preset positioning pin passes through the positioning holes 105, 305, 405 of the lead frame 100, the lead frame 300 and the lead frame 400 that are aligned with and overlapped with each other along the vertical direction.

The above detailed descriptions are provided to illustrate specific embodiments of the present invention and are not intended to be limiting. Numerous modifications and variations within the scope of the present invention are possible. The present invention is defined by the appended claims. 

What is claimed is:
 1. A power semiconductor device comprising: a die paddle, and a first semiconductor chip and a second semiconductor chip respectively attached to a front side and a back side of the die paddle; one or more conductive pads attached at the top surface of the first semiconductor chip and one or more conductive pads attached at the top surface of the second semiconductor chip; and a plastic package body covering the first semiconductor chip, the second semiconductor chip, the die paddle and the conductive pads, wherein at least one side surface of a conductive pad is exposed from one side surface of the plastic package body.
 2. The power semiconductor device of claim 1, wherein a side surface of the die paddle is coplanar with the side surface of the conductive pad exposing outside of the plastic package body, and thus the side surface of the die paddle and the side surface of the conductive pad are both exposed from the side surface of the plastic package body.
 3. The power semiconductor device of claim 1, wherein the die paddle is completely covered by the plastic package body.
 4. The power semiconductor device of claim 1, wherein a top surface of the at least one conductive pad attached at the top surface of the first semiconductor chip is exposed from the top surface of the plastic package body.
 5. The power semiconductor device of claim 1, wherein a top surface of the at least one conductive pad attached at the top surface of the first semiconductor chip is covered by the plastic package body.
 6. The power semiconductor device of claim 1, wherein a top surface of the at least one conductive pad attached at the top surface of the second semiconductor chip is exposed from the bottom surface of the plastic package body.
 7. The power semiconductor device of claim 1, wherein a top surface of the conductive pad attached at the top surface of the second semiconductor chip is covered by the plastic package body.
 8. The power semiconductor device of claim 1, wherein each of the one or more conductive pads are attached to each electrode at the respective top surfaces of the first semiconductor chip and the second semiconductor chip respectively, and the electrodes at the respective bottom surfaces of the first semiconductor chip and the second semiconductor chip are accordingly attached to the front side and the back side of the die paddle through a conductive material respectively.
 9. The power semiconductor device of claim 1, wherein a first conductive pad and a second conductive pad are attached on the two electrodes at the respective top surface of the first semiconductor chip or the second semiconductor chip, wherein the first conductive pad is thicker than the second conductive pad, and the first conductive pad is L shape with a notch formed at one corner thereof and the second conductive pad is arranged inside the notch.
 10. The power semiconductor device of claim 9, wherein a top surface of the first conductive pad attached at the top surface of the first semiconductor chip is exposed outside of the top surface of the plastic package body and the top surface of the first conductive pad attached at the top surface of the second semiconductor chip is exposed outside of the bottom surface of the plastic package body; and an L-shaped heat sink having a size and a shape similar with that of the first conductive pad is aligned with and attached to the top surface of the first conductive pad, and an extension part is perpendicular to and extends out at one side edge of the heat sink, wherein the side edge of the heat sink is flush with the side surface of the plastic package body.
 11. A preparation method of a power semiconductor device comprising: providing a first lead frame with a plurality of die paddles; attaching a first semiconductor chip to a front side of each die paddle; flipping the first lead frame with the first semiconductor chip attached on the die paddle and then attaching a second semiconductor chip to a back side of the die paddle; providing a second lead frame with a plurality of conductive pads to mount on the plurality of first semiconductor chips, wherein each conductive pad is attached on an electrode at a top surface of each first semiconductor chip; providing a third lead frame with a plurality of conductive pads to mount on the plurality of second semiconductor chips, wherein each of the conductive pad is attached on an electrode at a top surface of each second semiconductor chip; forming a plastic package layer covering the first lead frame, the second lead frame, the third lead frame, the first semiconductor chips and the second semiconductor chips; cutting a lamination between two adjacent die paddles, wherein the lamination comprises the first lead frame, the second lead frame, the third lead frame and the plastic package layer wherein a plastic package body, formed by cutting the plastic package layer, covers each die paddle, the first semiconductor chip and the second semiconductor chip attached on the die paddle, one or more conductive pads at the top surface of the first semiconductor chip and one or more conductive pads at the top surface of the second semiconductor chip, wherein one side surface of each conductive pad is exposed outside of one cutting side surface of the plastic package body.
 12. The method of claim 11, wherein electrodes at bottom surfaces of the first semiconductor chip and the second semiconductor chip are accordingly attached to the front side and the back side of the die paddle respectively.
 13. The method of claim 11, wherein a side surface of the conductive pad attached on the first semiconductor chip, a side surface of the conductive pad attached on the second semiconductor chip and a side surface of the die paddle are located in a co-plane, which are exposed outside of a side surface of the plastic package body obtained by cutting the lamination along the co-plane.
 14. The method of claim 11, wherein a side surface of the conductive pad attached on the first semiconductor chip and a side surface of the conductive pad attached on the second semiconductor chip are located in a co-plane, which are exposed outside of one side surface of the plastic package body obtained by cutting the lamination along the co-plane.
 15. The method of claim 11, wherein the plastic package body covers the top surface of the conductive pad.
 16. The method of claim 11, wherein a top surface of the conductive pad attached at the top surface of the first semiconductor chip is exposed outside the plastic package body.
 17. The method of claim 11, wherein a top surface of the conductive pad attached at the top surface of the second semiconductor chip is exposed outside of the plastic package body.
 18. The method of claim 11, wherein a first conductive pad and a second conductive pad are attached on two electrodes at the top surface of the first semiconductor chip or the second semiconductor chip, wherein the first conductive pas has an L shape with a notch formed at one corner thereof, and the second conductive pad is arranged inside the notch, and wherein the first conductive pad is thicker than the second conductive pad.
 19. The method of claim 18, wherein a top surface of a first conductive pad attached at the top surface of the first semiconductor chip is exposed outside of the top surface of the plastic package body and a top surface of the first conductive pad attached at the top surface of the second semiconductor chip is exposed outside of the bottom surface of the plastic package body; and an L-shaped heat sink having same size and shape similar with that of the first conductive pad is aligned with and attached to the top surface of the exposed first conductive pad, and an extension part perpendicular to the L-shaped heat sink extends out of one side edge of the L-shaped heat sink, wherein the side edge of the L-shaped heat sink is flush with the side surface of the plastic package body.
 20. A preparation method of a power semiconductor device comprising: providing a second lead frame with a plurality of conductive pads; flipping and mounting a plurality of first semiconductor chips on the second lead frame, wherein one conductive pad is aligned and attached on an electrode at a top surface of each first semiconductor chip; mounting a first lead frame with a plurality of die paddles on the plurality of first semiconductor chips, wherein an electrode at the bottom surface of each first semiconductor chip is aligned and attached to the back side of the die paddle; attaching each of a plurality of second semiconductor chips to a front side of each die paddle; providing a third lead frame with a plurality of conductive pads and mounting the third lead frame on the plurality of second semiconductor chips, wherein one conductive pad is aligned with and attached on an electrode at a top surface of each second semiconductor chip; forming a plastic package layer covering the first lead frame, the second lead frame, the third lead frame, the plurality of first semiconductor chips and the plurality of second semiconductor chips; cutting a lamination between two adjacent die paddles, wherein the lamination comprises the first lead frame, the second lead frame, the third lead frame and the plastic package layer; wherein a plastic package body formed by cutting the plastic package layer covers each die paddle and the attached first semiconductor chip and second semiconductor chip, one or more conductive pads attached at the top surface of the first semiconductor chip and one or more conductive pads attached at the top surface of the second semiconductor chip, wherein one side surface of each conductive pad is exposed outside of one cutting side surface of the plastic package body.
 21. The method of claim 20, wherein the side surface of the conductive pad attached on the first semiconductor chip, the side surface of the conductive pad attached on the second semiconductor chip and the side surface of the die paddle are located in a co-plane; and Wherein one cutting side surface of the plastic package body is formed by cutting the lamination along the co-plane, so that the side surface of the die paddle and the side surface of the conductive pads attached on the first semiconductor chip and second semiconductor chip are exposed outside of the cutting side surface of the plastic package body.
 22. The method of claim 20, wherein the side surface of the conductive pad attached on the first semiconductor chip and the side surface of the conductive pad attached on the second semiconductor chip are also located in a co-plane; and wherein one cutting side surface of the plastic package body is formed by cutting the lamination along the co-plane, wherein the side surface of the conductive pads attached on the first semiconductor chip and second semiconductor chip are exposed outside of the cutting side surface of the plastic package body. 